The present invention relates to the testing of an electronic system or subsystem having one or more integrated circuits, and more particularly to a method and apparatus for providing boundary scan testing for each integrated circuit that is a part of the system or sub-system. The new method and apparatus uses a system or sub-system parallel bus as the interface and control connection for each integrated circuit having boundary scan test circuitry.
The increasing use of very large scale integrated circuits, i.e. integrated circuits with greater than 100,000 active devices, has led to a testability problem of systems or sub-systems made up of VLSI circuits. The problem stems from the fact that one VLSI circuit typically has 100 to 200 input/output pins, but it contains more active devices than the most sophisticated electronic system of the previous generation. However, the previous generation system devices would have many thousands of pins at which various test measurements might be performed. The result then of having systems or sub-systems comprised of VLSI circuits performing highly sophisticated functional capabilities usually is decreased accessibility and testability with respect to their pre-VLSI counterparts.
This testability problem is aggravated further by the increasing use of application specific integrated circuits. ASICs combine multiple elemental functions within a single integrated circuit in order to perform a complex function. ASICs also save processing time that would otherwise be used shuttling signals between elemental function integrated circuits, thereby increasing performance. Furthermore, in large lots, ASICs have a lower cost than the total cost of the individual SSI/MSI/LSI components which each ASIC replaces. Therefore, the hardware trend towards the use of more complex ASICs also is a trend towards a lessening of system testability.
The VLSI/ASIC testability problem is further aggravated by the increasing use of high density integrated circuit mounting techniques, such as surface mount, tape automated bonding (TAB), chip-on-board (COB) and hybrid technology techniques, especially when used in conjunction with multi-layer circuit boards. The result being that very few input/output pins may be readily accessible by physical probing. But even when the input/output pins are physically accessible for testing, the input/output pin may be electrically connected to many other components (as in parallel address and data buses) and be very difficult to test independently.
The testability problem is not a minor one. Numerous manufacturers of complex electronic systems have recognized the need to locate and repair faulty components before and after those systems reach the customers. In-field repair inherently has higher costs because of the transportation expense of sending repair personnel and equipment to a customer's location, so any existing faults should be corrected before the system is sold. Further, the customer often is partially or totally idled by a faulty system, so the customer needs a system that can be fault diagnosed and repaired quickly. An inability to test and locate faulty components affects both the system manufacturer and the customer adversely.
One solution to the testability problem of complex and densely populated systems is known from a boundary scan technique proposed by an international industry group known as the joint test action group (JTAG). The JTAG boundary scan technique adds an input decoupling buffer and/or an output coupling buffer between each integrated circuit pin and the functional circuit that the pin normally connects to at both the physical and logical boundary of each integrated circuit using this technique. Each buffer has a register associated with it so each buffer is switchable between normal and test functions. In this manner, the buffers may be used to divide the system or sub-system into testable portions, or to receive or transmit signals to or from the integrated circuit pins. The proposed JTAG boundary scan technique interconnects each of the register circuits in series. This series connection requires at least two pins of the total pin complement of the integrated circuit package, and the usual configuration requires four pins to implement the typical JTAG boundary scan interconnections.
The JTAG solution, or any similar solution, to the testability problem which includes the addition of two or more dedicated test pins is undesirable because the number of pin connections available to connect the internal functionality with the external printed circuit board often is the greatest limitation faced by an integrated circuit designer. Each pin must have a pad area on the integrated circuit chip for connection to the pin. The more pads/pins that are required, the larger will be the required chip area. The larger the chip area, the smaller the quantity of chips which can be produced from each semiconductor wafer and the higher the cost per chip. This is purely a size limitation on a per square inch of substrate wafer basis, and does not include the cost of a lower yield inherent with larger integrated circuits because of an increased likelihood of one or more manufacturing flaws occurring. Nor does it include the increased expense of attaching the four dedicated test pins.
Therefore, it is an object of this invention to provide a method of providing increased testability using boundary scan registers and buffers in conjunction with a parallel system or sub-system bus.
It is another object of this invention to provide a method of providing boundary scan testing without the addition of any pins/connection which are dedicated to testing.
It is a further object of the invention to provide an apparatus for providing increased testability using boundary scan registers and buffers in conjunction with a parallel system or sub-system bus.
It is yet another object of the invention to provide an apparatus for providing boundary scan testing without the addition of any external pins/connections which are dedicated solely to testing or controlling existing pins to operate uniquely when configured in a special test mode of operation, such as multiplexing or level shifting.
It is yet a further object of the invention to provide an apparatus which decreases the time required to perform boundary scan testing.